Silicon-on-insulator (SOI) integrated-circuit (IC) technology offers performance advantages over bulk-silicon or epitaxial-silicon IC technologies for commercial and military applications. SOI ICs can operate at higher speeds and lower power levels than equivalent bulk-silicon ICs, making the SOI ICs particularly useful for mobile communication and high-speed computer applications. These SOI ICs are also less prone to single-event upset (SEU) due to energetic cosmic particles which is important for deployment in outer space, in high-altitude aircraft, or in terrestrial systems.
Single-event upset can lead to system performance degradation or failure in space systems, and is becoming an increasing system reliability concern even in terrestrial systems. To SEU-harden bulk-silicon ICs to high cosmic ray levels, performance-degrading and/or area-degrading radiation hardening techniques must be currently used. Thus, SEU-hardened bulk-silicon ICs may not be compatible with future advanced complementary-metal-oxide-semiconductor (CMOS) technologies.
Silicon-on-insulator ICs can also function without upset or failure after exposure to extremely high dose-rate pulses of ionizing radiation. It is impossible to fabricate bulk-silicon ICs that can function at radiation dose levels achievable by properly designed SOI ICs. These radiation-hardness properties make SOI devices attractive for space and weapon applications. Because of the high levels of SEU and dose-rate radiation hardness obtainable by SOI circuits, system applications heretofore unimaginable with bulk-silicon ICs can be realized. However, the total-dose hardening of SOI devices is much more difficult than for bulk-silicon ICs due to a back-channel leakage current resulting from charge trapping in an oxide layer buried below the SOI devices.
The primary factor that leads to the SEU and dose-rate advantages of SOI technology over bulk-silicon technology is that SOI transistors are built in a thin silicon active layer (also termed a device layer) above a buried silicon dioxide (SiO.sub.2) layer (also termed a buried oxide layer) rather than in a bulk silicon wafer. The SOI device layer is typically about 50-200 nanometers thick, compared to a thickness of about 725 .mu.m for a bulk silicon wafer. In a conventional thin-film SOI field-effect transistor or complementary field-effect transistor pair (i.e. an inverter), a source region and a drain region are formed to extend completely through the device layer to the buried oxide below. Transistors in a bulk-silicon IC are formed in n-type or p-type wells that have been ion implanted into the wafer. The SEU hardness of an IC can be related to the charge collected after a cosmic-ray strike. For a bulk-silicon CMOS transistor, charge can be collected from a region several microns deep in the silicon wafer. On the other hand, for an SOI transistor, only the charge deposited within the very thin device layer is collected since the buried oxide layer electrically isolates the device layer from the remainder of the wafer. This provides a higher degree of SEU hardness for SOI devices than for bulk-silicon devices. Furthermore, the dose-rate hardness of an SOI device is superior to a bulk-silicon device since the SOI device has considerably less p-n junction area than the bulk-silicon device because the dose-rate hardness of an IC is related to the total p-n junction area of the IC.
Despite the inherent dose-rate and SEU hardness advantage of SOI technology, two factors can reduce the radiation hardness of SOI circuits. These two factors are floating body effects that degrade SEU and dose-rate hardness, and back-channel leakage that degrades total-dose ionizing radiation hardness. For a partially-depleted SOI transistor, the silicon depletion region does not extend completely through the device layer so that a thin silicon body region exists between the edge of the silicon depletion region and the silicon/buried oxide interface and between the source and drain of the transistor. In normal operation of the SOI transistor as a three-terminal device, this silicon body region is not tied to a specific electrical potential, but is instead floating. Thus, any charge generated within the body region by a cosmic ray strike can cause a reduction in a potential barrier between the source and the body region (i.e. a source-to-body potential). Similarly, electrical charge generated by impact ionization due to an increased current flow as a result of exposure to a high dose-rate pulse of ionizing radiation can cause a reduction in the source-to-body potential. As a result, a parasitic bipolar transistor effect can be initiated that can significantly increase the collected electrical charge. The magnitude of floating body effects can be sufficient to cause reliability degradation due to soft errors in conventional SOI transistors due to terrestrial cosmic rays. To prevent such floating body effects, body ties can be used to tie or electrically connect the body potential to a fixed electrical potential, generally at the same potential as the transistor source. Unfortunately, these body ties can significantly increase the size of the transistors so that most commercial SOI circuit designs use body ties only at critical locations.
The total-dose hardening of SOI ICs is more difficult than hardening bulk-silicon ICs due to the presence of the SOI buried oxide layer. Total-dose ionizing radiation-induced back-channel leakage occurs as positive electrical charge is trapped in the buried oxide near the bottom silicon/buried oxide interface. Typical SOI buried oxides contain numerous defects that result in considerable radiation-induced charge trapping. As charge is trapped in the buried oxide, the overlying silicon becomes inverted at the silicon/buried oxide interface, thereby forming a back-channel leakage current path between the transistor source and drain (see FIG. 3b). The back-channel leakage current can be substantial even at low levels of total-dose ionizing irradiation (see FIG. 3a), and can severely limit the lifetime of conventional SOI ICs in space systems. Techniques have been developed to fabricate hardened SOI buried oxides to minimize radiation-induced positive charge buildup near the back-channel interface. Unfortunately, the present processing techniques used to fabricate radiation hardened buried oxides are expensive to implement, are difficult to control, and are not compatible with standard IC processing equipment.
An advantage of the present invention is that a radiation-hardened SOI field-effect transistor can be fabricated with a significantly reduced radiation-induced back-channel leakage current, while retaining the SEU and dose-rate hardness advantages inherent to thin-film SOI technology.
A further advantage of the present invention is that the SOI field-effect transistor can be formed with a body tie contact extending along an entire conducting channel of the transistor, thereby reducing floating body effects during operation of the transistor.
Yet another advantage of the SOI field-effect transistor having the body tie contact is that the body tie contact can be formed without a significant increase in the area of the transistor.
Still another advantage of the SOI field-effect transistor having the body tie contact is that the body tie contact improves radiation hardening of the transistor, and in particular the single-event-upset hardening of the transistor.
A further advantage is that the SOI field-effect transistor of the present invention provides an improvement over conventional SOI transistors for terrestrial applications (e.g. consumer applications) as well as for space applications.
Yet another advantage of the present invention is that a radiation-hardened SOI integrated circuit can be fabricated comprising one or more complementary pairs of SOI field-effect transistors.
Still another advantage is that the SOI field-effect transistor of the present invention can be formed using a conventional SOI wafer without the need for a SOI wafer having a specially prepared hardened buried oxide layer.
A further advantage of the present invention is that the SOI field-effect transistor of the present invention has an improved radiation hardness to provide a prolonged lifetime in harsh environments.
These and other advantages of the present invention will become evident to those skilled in the art.